<div class="content-intro"><p data-renderer-start-pos="41">K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.</p> <p data-renderer-start-pos="570">The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.</p> <p data-renderer-start-pos="994">With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.</p></div><p><strong><span data-contrast="auto">About the Role</span></strong> <br><span data-contrast="auto">We are looking for a hands-on Senior SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs.</span></p> <p><span data-contrast="auto">You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up.</span></p> <p><strong><span data-contrast="auto">Responsibilities</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li><span data-contrast="auto">Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Perform BER and stress testing across representative and worst-case channels.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Support the transition from chip-level SerDes characterization to product integration and system-level validation.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.</span> </li> </ul> <p><strong><span data-contrast="auto">Qualifications</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li><span data-contrast="auto">BS/MS in Electrical Engineering, Computer Engineering, or related field.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.</span><span data-ccp-props="{"335559739":0}"> </span></li> <li><span data-contrast="auto">Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.</span><span data-ccp-props="{"3355597