<p><strong><span data-contrast="auto">About Graphcore</span></strong><span data-ccp-props="{}"> </span></p> <p>At Graphcore, we’re building the future of AI compute.</p> <p>We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.</p> <p>As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.</p> <p>To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.</p> <p>We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.</p> <p><strong><span data-contrast="auto">Job Summary</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">We are seeking a Director of Silicon Logical Design to lead and scale our Logical Design group within the Silicon department. This role is accountable for the overall strategy, technical direction, execution quality and team development for Graphcores microarchitecture and RTL design efforts.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">The Director will be responsible for ensuring that our logical design methodologies, architectures and RTL implementations meet world class standards for performance, power, area, and schedule. This leader will partner closely with Architecture, Physical Design, Verification, DFT and Program Management teams to ensure successful, predictable silicon delivery aligned with Graphcores long term product roadmap.</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">The Team</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">The Logical Design team deliver the micro-architecture and RTL that realise our advanced chip architectures. As Director, you will guide this multi site team, strengthen cross functional collaboration, and drive the evolution of our design flows and capabilities.</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Responsibilities and Duties</span></strong><span data-ccp-props="{}"> </span></p> <p><em><span data-contrast="auto">Leadership & Strategy</span></em><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="1"><span data-contrast="auto">Define and execute the strategic roadmap for Logical Design, ensuring alignment with Graphcores silicon and product strategy.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Lead, grow and mentor a high performing RTL/micro architecture design organisation.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Establish and implement best in class design methodologies, documentation standards and quality metrics.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Drive continuous improvement across team structure, workflows, tooling, and design processes.</span><span data-ccp-props="{}"> </span></li> </ul> <p> </p> <p><em><span data-contrast="auto">Technical Ownership</span></em><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":720,"469769226":"Aptos","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Provide technical oversight of micro architecture specification and RTL development across all major blocks and subsystems.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Aptos" data-listid="2" data-lis