Mixed Signal IC Layout Engineer

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p><span style="font-size: 10pt;">Tenstorrent is looking for a Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.</span></p> <p><span style="font-size: 10pt;">This role is<strong> remote,</strong> based out of any in the <strong>United States.</strong></span></p> <p><span style="font-size: 10pt;">We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</span></p> <p> </p> <h2 style="line-height: 1.2;"><span style="font-size: 10pt;"><strong>Who you are</strong></span></h2> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.</span></li> </ul> <h2 style="line-height: 1.2;"><span style="font-size: 10pt;"><strong>What we need</strong></span></h2> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.</span></li> </ul> <h2 style="line-height: 1.2;"><span style="font-size: 10pt;"><strong>What you will learn</strong></span></h2> <ul> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Deep, hands-on experience with cutting-edge FinFET technologies (down to 2nm) and the nuances of mixed-signal layout at these nodes.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">How to integrate high-speed analog/mixed-signal IP into a complex D2D PHY, including interactions across digital, analog, and I/O domains.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">Advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments.</span></li> <li style="font-size: 10pt;"><span style="font-size: 10pt;">How to influence and evolve layout flows, methodologies, and automation, shaping how the broader team delivers high-quality silicon.</span></li> </ul> <p style="line-height: 1.2;"> </p> <p><em>Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.</em></p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.