Senior Embedded Performance Engineer

<div class="p-rich_text_section"> <div class="layout-content"> <div class="notion-selectable notion-page-block" data-block-id="14b2905b-d614-8006-a80f-dc58ff451e32"> <h2><strong>About Fractile</strong></h2> <p>Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.</p> <p>The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems. </p> <h3><span style="font-size: 12pt;"><strong>The Role</strong></span></h3> <p><span style="font-size: 12pt;">On the device, close to the metal, we write the runtime software that orchestrates work across the chip and runs performance-critical ML kernels. This is where performance gets real and the wins compound. Your work directly influences trade-offs for the silicon, system deployment, and the compiler.</span></p> <p><span style="font-size: 12pt;">You'll drive the first accelerator compute runs, evaluating performance on silicon, running early benchmarks, and feeding results back into the hardware and software roadmap.</span></p> <h3><span style="font-size: 12pt;"><strong>What you’ll do</strong></span></h3> <ul> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Write and optimise performance-critical ML kernels in C, with assembly where it matters (RISC-V and our own ISA)</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Build the low-level control paths that feed those kernels, including scheduling, synchronisation, and data movement</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Write targeted validation workloads and microbenchmarks to keep simulation and hardware behaviour aligned and performance measurable.</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Profile, benchmark, and track regressions so performance improvements are real and repeatable</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Work closely with simulation, hardware, ML, compiler, firmware, and runtime engineers in a tight loop, turning profiling data into architecture feedback and real performance wins.</span></li> </ul> <h3><span style="font-size: 12pt;"><strong>What we’re looking for</strong></span></h3> <ul> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Proven deeply embedded software experience</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Strong performance instincts. You can reason about low-level architecture, memory behaviour, and where the cycles are spent</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Excellent C, and a pragmatic approach to building high-quality, maintainable low-level code</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Comfortable writing and debugging optimised assembly (RISC-V ideal)</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Collaborative and high-ownership. You communicate clearly, move fast, and enjoy working through hard problems with others</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Computer Science, Electronic Engineering, Maths, Physics, or related degree and 3+ years of industry experience</span></li> </ul> <h3><span style="font-size: 12pt;"><strong>Nice to have</strong></span></h3> <ul> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Experience with GPUs or dedicated ML accelerators</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Rust and/or Python experience</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Experience with simulators (functional or performance) and writing validation or benchmarking workloads</span></li> <li style="font-size: 12pt;"><span style="font-size: 12pt;">Familiarity with modern ML inference workloads</span></li> </ul> <p><span style="font-size: 12pt;">If you want to build the software that turns cutting-edge hardware capability into real throughput and low latency, come build it with us.</span></p> <h2><strong>What We Offer</strong></h2> <ul> <li>Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.</li> <li>Equity & Ownership: meaningful equity so everyone shares in the value creation</li> <li>Benefits: Private Medical, Dental and Vis