andurilindustries · Costa Mesa, California, United States · Costa Mesa, California, United States
<div class="content-intro"><p>Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.</p></div><p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 3">ABOUT THE TEAM</span></span></strong><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":281,"335559739":281}"> </span></p> <p><span data-contrast="auto">The Air Dominance and Strike (AD&S) Electrical Engineering Team develops high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms. Working across hardware, software, and mission autonomy, the team delivers flight-critical electronics, PCB assemblies, and FPGA-based processing architectures for Anduril's next-generation autonomous air platforms. AD&S Electrical Engineers drive end-to-end development, from system architecture and circuit design through verification, integration, and flight test, delivering mission-ready systems that meet demanding performance, reliability, and survivability requirements.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 3">ABOUT THE JOB </span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":281,"335559739":281}"> </span></strong></p> <p><span data-contrast="auto">We are looking for an <strong>FPGA Design Engineer</strong> to join our team in Costa Mesa, CA. In this role, you will design and integrate RTL for FPGA and SoC platforms used in high-performance embedded systems, avionics, and mission-critical hardware. You will work across the full development cycle, from requirements and microarchitecture through RTL implementation, simulation, synthesis, timing closure, lab bring-up, and system integration.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><span data-contrast="auto">We welcome candidates from a range of complex digital hardware environments.</span><span data-ccp-props="{"335559738":240,"335559739":240}"> </span></p> <p><strong><span data-contrast="none"><span data-ccp-parastyle="heading 4">WHAT YOU'LL DO</span></span><span data-ccp-props="{"134245418":true,"134245529":true,"335559738":319,"335559739":319}"> </span></strong></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA and SoC-based systems.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Translate system and hardware requirements into microarchitecture, interface definitions, and implementation plans.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Own FPGA designs or major functional blocks from architecture through integration, timing closure, and lab debug.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Develop and execute simulation, synthesis, and implementation flows, including timing and resource closure.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Debug functional, timing, and integration issues in simulation and on hardware.</span><span data-ccp-props="{"335559739":0}"> </span></li> </ul> <ul> <li data-leveltext="" data-font=