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Engineering Manager - FPGA & Hardware - Enforced Security

opswat · Tampa, Florida, United States · Tampa, Florida, United States
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<div class="content-intro"><p><span class="acronym-highlight">OPSWAT</span>, a global leader in IT, <span class="acronym-highlight">OT</span>, and <span class="acronym-highlight">ICS</span> critical infrastructure cybersecurity, delivers an end-to-end platform that gives public and private sector organizations and enterprises the critical advantage needed to protect their complex networks, secure their devices, and ensure compliance. Over the last 20 years our commitment to innovative technology has earned the trust of more than 1,700 organizations, governments, and institutions globally, solidifying our role in protecting the world’s critical infrastructure and securing our way of life.</p></div><p><strong><span data-contrast="none">Role Summary</span></strong><span data-ccp-props="{"335559738":320,"335559739":120}"> </span></p> <p><span data-contrast="none">MetaDefender NetWall is OPSWAT's hardware-enforced boundary between networks that must never be able to talk back — a combined hardware and software product deployed across critical infrastructure, defense, and government. This role builds the layer that makes that guarantee physical rather than declared: protocol termination, one-way transport, and content filtering enforced in FPGA (Field-Programmable Gate Array) silicon, at rates no general-purpose processor can sustain.</span><span data-ccp-props="{"335559738":70,"335559739":150}"> </span></p> <p><span data-contrast="none">The Engineering Manager owns the FPGA discipline end to end — silicon and board selection, RTL (Register-Transfer Level) architecture, verification strategy, timing closure, toolchains, IP (Intellectual Property) licensing, the bring-up lab, and the team that does the work — and partners daily with software engineering, product, certification, QA (Quality Assurance), manufacturing, and supply chain. Success in the first twelve months means a working hardware datapath, a verified first protocol running in gateware, and an FPGA team that did not exist before — not the volume of RTL written.</span><span data-ccp-props="{"335559738":70,"335559739":150}"> </span></p> <p><strong><span data-contrast="none">What Comes With the Role</span></strong><span data-ccp-props="{"335559738":320,"335559739":120}"> </span></p> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":431,"335559991":259,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">An installed base across energy, manufacturing, defense, government, transportation, and healthcare, already running on the NetWall unidirectional and bilateral security gateways</span><span data-ccp-props="{"335559738":60,"335559739":60}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":431,"335559991":259,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="none">An existing Common Criteria EAL4+ certification to extend rather than earn, and certified optical isolation hardware already in the product</span><span data-ccp-props="{"335559738":60,"335559739":60}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":431,"335559991":259,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="none">An R&D (Research and Development) organization of approximately 50 engineers, and the MetaDefender® platform — Multiscanning, Deep CDR™ Technology, Proactive DLP™ Technology, and policy enforcement — to build on rather than replicate</span><span data-ccp-props="{"335559738":60,"335559739":60}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":431,"335559991":259,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">A funded multi-year program to take the line to 100 Gbps and to NCDSMO (National Cross Domain Strategy and Management Office) Raise the Bar</span><span data-ccp-props="{"335559738":60,"335559739":60}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":431,"335559991":259,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="none">Budget and hiring authority to build the FPGA team from the first engineer, outside the standard requisition process</span><span data-ccp-props="{"335559738":60,"335559739":60}"> </span></li> </ul> <p><strong><span data-contrast="none">Key Responsibilities</span></strong><span data-ccp-props="{"335559738":320,"335559739":120}"> </span></p> <ul> <li data-leveltext="•" data-font="" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":431,"335559991":259,"469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="none">Own the FPGA discipline for the NetWall line — RTL architecture, verification st

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