๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐ ๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ญ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฎ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ญ๐ฑ-๐ฎ๐ฑ ๐๐ฃ๐) Experience: 8+ yrs Location: Banglore We are looking for an experienced AMS Verification Lead with strong hands-on expertise in Analog/Mixed-Signal (AMS) verification, SystemVerilog, UVM, and Real Number Modeling (RNM). The ideal candidate will lead verification activities for mixed-signal IPs, develop robust verification environments, drive functional coverage closure, and ensure high-quality verification sign-off. This role requires a strong understanding of analog-digital interactions, verification methodologies, simulation workflows, and semiconductor design processes. The successful candidate will combine technical depth with ownership of verification planning, execution, debugging, and team collaboration. Requirements Key Responsibilities โข Lead end-to-end verification of analog and mixed-signal IPs, ensuring functional correctness and verification readiness. โข Develop comprehensive verification plans, test strategies, testbenches, and verification methodologies based on design specifications. โข Build, maintain, and enhance SystemVerilog and UVM-based verification environments. โข Develop, integrate, and validate Real Number Models (RNM) for analog blocks and mixed-signal verification. โข Verify interactions between analog and digital components, including interface behaviour, signal transitions, and functional dependencies. โข Perform functional coverage analysis, identify coverage gaps, debug simulation failures, and drive coverage closure. โข Verify mixed-signal IPs such as ADCs, DACs, PLLs, oscillators, and LDOs. โข Manage simulation regressions, track verification schedules, monitor deliverables, and support verification sign-off. โข Collaborate with analog design, digital design, SoC verification, and other engineering teams to resolve technical issues. โข Investigate verification failures, perform root-cause analysis, and recommend corrective actions. โข Maintain verification documentation, test results, coverage reports, and technical sign-off records. โข Identify opportunities to improve verification efficiency through automation, reusable components, and better workflows. โข Provide technical leadership, review verification approaches, and mentor engineers on AMS verification best practices. What Makes You a Great Fit โข 8+ years of experience in semiconductor verification, with substantial hands-on experience in Analog/Mixed-Signal verification. โข Strong proficiency in SystemVerilog and UVM for developing and maintaining verification environments. โข Practical experience with Real Number Modeling (RNM) and mixed-signal verification methodologies. โข Strong understanding of analog-digital interface verification and mixed-signal simulation concepts. โข Experience verifying analog or mixed-signal IPs such as ADCs, DACs, PLLs, oscillators, and LDOs. โข Proven skills in simulation debugging, functional coverage analysis, regression management, and verification sign-off. โข Ability to independently own verification planning, execution, issue resolution, and technical deliverables. โข Familiarity with tools such as Cadence Virtuoso, AMS Designer, or equivalent AMS simulation platforms. โข Knowledge of analog behavioural modelling and SystemVerilog-AMS is an advantage. โข Experience with semiconductor IP verification or SoC-level verification is desirable. โข Proficiency in Python or Tcl scripting for verification automation is a plus. โข Strong analytical, debugging, and problem-solving skills with excellent attention to detail. โข Effective communication and collaboration skills across multidisciplinary engineering teams. โข Previous experience mentoring verification engineers or leading technical activities is preferred.