<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg" data-pm-slice="1 1 []"><strong>Role Overview</strong></p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize real silicon in the lab, and drive root-cause analysis of the toughest system-level issues.</p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">As AI workloads scale into rack-level infrastructure, every link has to perform flawlessly. Your work will directly shape the quality, performance, and time-to-market of the products that connect the world's most advanced AI platforms, in a hyper-growth company where your technical judgment carries real weight.</p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Key Responsibilities</strong></p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Post-Silicon Validation Leadership</strong></p> <ul> <li>Architect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production release</li> <li>Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams</li> <li>Lead lab bring-up of new silicon, including board, firmware, and software readiness</li> </ul> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Debug and Characterization</strong></p> <ul> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Characterize high-speed serial link performance, including margining, signal integrity, and compliance, across process, voltage, and temperature</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Partner with design and DFT teams to feed findings back into current and future product generations</li> </ul> <p><strong>Automation and Infrastructure</strong></p> <ul> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Develop scalable validation automation frameworks and test content using Python and C/C++</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughput</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Analyze large validation datasets to identify trends, outliers, and risks early</li> </ul> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Technical Leadership</strong></p> <ul> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Mentor engineers and set best practices for validation methodology across the team</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Collaborate with customers and Field Applications Engineers to reproduce and resolve system-level issues</li> </ul> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Basic Qualifications</strong></p> <ul> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Strong scripting and programming skills in Python and/or C/C++ for test automation</li> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Proven ability to debug complex hardware and firmware issues to root cause</li> </ul> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Preferred Qualifications</strong></p> <ul> <li class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Master's degree or PhD in Electri