This role is for one of Weekday’s clients Min Experience: 8+ years Location: Bengaluru, Noida JobType: full-time Own DFT for a full SoC. Derive the DFT architecture with the customer and product engineering teams, lead a team of 4–6 engineers, drive DFT sign-off, and support silicon bring-up. Experience: 8 to 9 years. Must have 5 or more tapeouts, with at least 1 as DFT lead. Requirements Desired Skills: 1. Defines SoC DFT architecture against test time, test cost, coverage, test power and pin budget. 2. Exposure to streaming scan networks (SSN) or tile-based hierarchical DFT for large SoCs. 3. Applies advanced fault models: cell-aware, path delay, small delay defect and IDDQ. 4. Owns SoC-wide MBIST and repair architecture, including shared-bus memory test. 5. Low-power DFT: power-domain aware scan and test-mode power management (UPF-aware DFT). 6. Owns DFT-mode STA sign-off criteria with the STA team. 7. Leads post-silicon work: ATE bring-up, failing-pattern diagnosis and yield diagnosis support. 8. Owns schedule, effort estimates, risk tracking and weekly status to the customer. 9. Leads DFT plan and sign-off reviews, and interviews candidates. 10. LBIST and in-system test for automotive (ISO 26262) is a plus. Must-have skills DFT, SoC, tapeout Good-to-have skills DFT architecture, streaming scan networks, tile-based hierarchical DFT