<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p></p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Role Overview</strong></p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout.</p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms.</p> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Key Responsibilities</strong></p> <ul class="wnfdntj"> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Technical Leadership and Team Execution</strong></p> <ul class="wnfdntj"> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Define and evolve physical design methodologies, flows, and best practices across the team</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Physical Implementation</strong></p> <ul class="wnfdntj"> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management</p> </li> </ul> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Cross-Functional Collaboration</strong></p> <ul class="wnfdntj"> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Contribute to hiring, onboarding, and professional development of team members</p> </li> </ul> </li> </ul> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg"><strong>Basic Qualifications</strong></p> <ul class="wnfdntj"> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">10+ years of hands-on experience in physical design of complex SoCs or ASICs</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Proven experience leading projects and technical teams through one or more full-chip tapeouts</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre)</p> </li> <li class="wnfdnte _1ibi0s35c"> <p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Strong knowledge of timing closure, power/clock distribution, and physical veri