Director of ASIC Design Verification

<div class="content-intro"><p style="text-align: left;"><span style="font-size: 12pt;">SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.</span></p></div><h3><strong>About the team</strong></h3> <div data-perf-region="transcript" data-find-provider-scope=""> <div data-sizer-excess="0" data-rocksteady-sizer="" data-testid="transcript-sizer"> <div data-rs-index="15" data-index="15" data-testid="transcript-row" data-last-message="true"> <div class="rounded-lg focus-visible:shadow-focus focus-visible:outline-hidden"> <div data-test-render-count="1"> <div class="group group/message-row"> <div class="group relative relative pb-[var(--msg-assistant-pb,0.75rem)]" data-is-streaming="false"> <div class="font-claude-response relative leading-[1.65rem] [&_pre>div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8"> <div> <div class="standard-markdown grid-cols-1 grid [&_>_*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown"> <p class="font-claude-response-body break-words whitespace-normal">The DV team verifies SambaNova's RDU chips before they tape out. That covers block, full-chip, and gate-level benches, performance verification, coverage closure, and emulation and FPGA prototyping. When first silicon comes back, the same engineers debug bring-up in the lab.</p> </div> </div> </div> </div> </div> </div> </div> </div> </div> </div> <div data-testid="transcript-trailing"> <div class="flow-root"> <div> <div class="ml-[calc(var(--msg-text-inset,0.5rem)_-_0.25rem)] mt-6 flex items-center transition-transform duration-300 ease-out"> <div class="p-1 -translate-x-px" data-testid="chat-footer-spark"><span id="_r_bj_" class="inline-flex" data-base-ui-tooltip-trigger=""></span></div> </div> </div> </div> </div> <h3><strong>About the role</strong></h3> <p class="font-claude-response-body break-words whitespace-normal">SambaNova Systems is looking for a Director of ASIC Design Verification to own end to end verification for the next generation of our RDU chips. This role asks for genuine depth in verification, not just management of it. You'll be the technical authority on methodology as well as the leader of the team.</p> <p class="font-claude-response-body break-words whitespace-normal">You'll set verification architecture and strategy across the full chip and be accountable for pre-silicon quality through tape-out. The work spans block through full-chip and gate-level benches, performance verification, coverage closure, and emulation and FPGA prototyping. You'll be the DV voice in roadmap and tape-out readiness decisions, and your ownership carries into first silicon, supporting functional validation and bring-up debug in the lab.</p> <p class="font-claude-response-body break-words whitespace-normal">You'll lead an experienced team of 8-10 engineers, including principal-level engineers who have built and evolved our verification environment across several generations of silicon. That depth is the most valuable thing you inherit. You'll own where the environment goes next, including the decision to change it, and we expect you to arrive with a point of view. You'll also own the team's growth, leveling, and technical bar as our silicon roadmap scales.</p> <h3><strong>Responsibilities</strong></h3> <p><strong>Own verification through tape-out</strong></p> <ul> <li>Own pre-silicon functional and performance verification for SambaNova ASICs — quality, coverage closure, and on-time delivery to tape-out</li> <li>Define verification architecture, strategy, schedules, and DV environments for complex, high-performance machine learning ASICs</li> <li>Serve as the technical authority on verification: arbitrate testbench architecture, set coverage and sign-off criteria, and lead debug on the hardest failures</li> <li>Set and defend the DV schedule and own tape-out readiness sign-off, including the trade-off between coverage depth and time to silicon; report risk and readiness to executive staff with a clear point of view, not just a dashboard</li> <li>Carry ownership into first silicon — support lab functional validation and bring-up debug, feeding findings back into the pre-silicon environment</li> </ul> <p><strong>Lead and grow the team</strong></p> <ul> <li>Bring a strong point of view on methodology, and be willing to disagree with the team and with peers when the engineering case supports it</li> <li>Own the direction of an established verification environment — understand the re