Principal Post-Silicon Validation Engineer

<div class="content-intro"><p style="text-align: left;"><span style="font-size: 12pt;">SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.</span></p></div><h3><strong>About the team</strong></h3> <p>We're the team behind post-silicon bring-up, debug, and validation for the high-speed IO and memory subsystems in SambaNova's DataScale platform. We own the path from first silicon power-on through field deployment: characterization, stress testing, performance validation, and root-causing issues across silicon, board, and software. We work directly with design, firmware, verification, and system engineering to keep bring-up on schedule, and partner with customer engineering on deployment and RMA debug. We build our own debug tooling and automation, and apply what we learn to pre-silicon verification to improve coverage on future programs.</p> <h3><strong>About the role</strong></h3> <div data-perf-region="transcript" data-find-provider-scope=""> <div data-sizer-excess="0" data-rocksteady-sizer="" data-testid="transcript-sizer"> <div data-rs-index="27" data-index="27" data-testid="transcript-row" data-last-message="true" data-perf-row="assistant" data-perf-row-from-tail="0" data-perf-row-streaming="false"> <div class="rounded-lg focus-visible:shadow-focus focus-visible:outline-hidden"> <div data-test-render-count="1"> <div class="group group/message-row"> <div class="group relative relative pb-[var(--msg-assistant-pb,0.75rem)]" data-is-streaming="false"> <div class="font-claude-response relative leading-[1.65rem] [&_pre>div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8"> <div> <div class="standard-markdown grid-cols-1 grid [&_>_*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown"> <p class="font-claude-response-body break-words whitespace-normal">SambaNova is seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale. You'll lead system-level debug across silicon, board, and software layers, driving issues to root cause from first silicon through field deployment. This is a hands-on role for an engineer with deep expertise in high-speed interfaces and hardware debug, who can operate in ambiguity and execute with high ownership.</p> </div> </div> </div> </div> </div> </div> </div> </div> </div> </div> <div data-testid="transcript-trailing"> <div class="flow-root"> <div> <div class="ml-[calc(var(--msg-text-inset,0.5rem)_-_0.25rem)] mt-6 flex items-center transition-transform duration-300 ease-out"> <div class="p-1 -translate-x-px" data-testid="chat-footer-spark"><span id="_r_ae_" class="inline-flex" data-base-ui-tooltip-trigger=""></span></div> </div> </div> </div> </div> <h3><strong>Responsibilities</strong></h3> <ul> <li>Own post-silicon bring-up and validation of high-speed IO and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis</li> <li>Establish power-on readiness ahead of first silicon, including debug infrastructure, tooling, and contingency planning</li> <li>Lead system-level debug to root cause complex issues spanning silicon, board, and software layers</li> <li>Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule</li> <li>Partner with system and customer engineering teams on product validation, deployment, and RMA debug</li> <li>Own validation sign-off for product release against stability, performance, and field reliability targets</li> <li>Review SoC and board design and SI/PI analysis through a post-silicon debug and deployment lens</li> <li>Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage</li> <li>Build scripts and tooling that automate validation, debug, and data analysis, and scale test coverage across systems</li> <li>Advance post-silicon validation methodology and debug infrastructure across programs</li> </ul> <h3><strong>Required qualifications</strong></h3> <ul> <li>M.S. in Electrical Engineering, Computer Science, or a related field</li> <li>7+ years of experience in post-silicon validation or system bring-up</li> <li>Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe</li> <li>Proven ability to lead cross-