Principal RTL Design Engineer

<div class="content-intro"><p style="text-align: left;"><span style="font-size: 12pt;">SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.</span></p></div><h3><strong>About the team</strong></h3> <div data-rs-index="98" data-index="98" data-testid="transcript-row" data-perf-row="human" data-perf-row-from-tail="1" data-perf-row-streaming="false"> <div class="rounded-lg focus-visible:shadow-focus focus-visible:outline-hidden"> <div data-test-render-count="2"> <div class="mb-1 mt-[var(--msg-gap,1.5rem)] group group/message-row"> <div class="flex flex-col items-end gap-1"> <div class="group/message-row flex min-w-0 flex-col items-end gap-xs font-sans ms-auto max-w-[85%] cds-um-enter" data-cds="UserMessage"> <div class="relative flex max-w-full min-w-0 flex-col gap-xs rounded-card px-lg py-md text-heading break-words select-text text-primary bg-neutral"> <div id="_r_3l0_" class=""> <div class="grid grid-cols-1 gap-2 relative [&_ul]:!space-y-0 [&_ol]:!space-y-0 [&_ul]:pl-8 [&_ol]:pl-8" data-testid="user-message"> <p>The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design.</p> </div> </div> </div> </div> </div> </div> </div> </div> </div> <h3><strong>About the role</strong></h3> <p>SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This is a senior individual contributor role where you'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, owning the power, performance, and area trade-offs along the way. Frequency targets are aggressive, so how you pipeline a datapath and where you spend area to buy timing are essential aspects of the role.</p> <h3><strong>Responsibilities</strong></h3> <ul> <li>Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems</li> <li>Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle</li> <li>Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring</li> <li>Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent</li> <li>Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures</li> <li>Work with architects and software teams to prototype and evaluate features that improve application-level performance</li> <li>Drive AI, automation, and new EDA tool methodologies into the design flow</li> <li>Set the technical bar in design reviews and mentor design engineers</li> </ul> <h3><strong>Required Qualifications</strong></h3> <ul> <li>B.S. in Electrical Engineering, Computer Engineering, or Computer Science</li> <li>7+ years of industry experience in ASIC RTL design</li> <li>Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent</li> <li>High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets</li> <li>Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures</li> <li>Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC</li> <li>Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team</li> <li>Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows</li> <li>Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers</li> <li>Scripting in Python for design and flow automation</li> </ul> <h3><strong>Preferred Qualifications</strong></h3> <ul> <li>M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science</li> <li>Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem</li> <li>Industry-standard interconnects and protocols including AXI, P