<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <h1 class="wnfdnti _1ibi0s33y _1ibi0s34u" data-pm-slice="1 1 []">Principal SerDes Bring-up Validation Engineer </h1> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Role Overview</h2> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer to join a cutting-edge mixed-signal design team and lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up and characterization strategies from the ground up, translating design and product requirements into measurable test objectives, pass/fail criteria, and schedules, and driving hands-on lab work to verify silicon against specification and performance targets.</p> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">As a hyper-growth company building the purpose-built connectivity that powers rack-scale AI infrastructure, the speed and rigor of our silicon validation directly shape what we can ship. You will partner closely with AMS design, firmware, and system teams to build automated test frameworks, debug complex analog and digital interactions at the physical layer, and deliver clear, data-driven recommendations that influence product direction. This is a high-impact role for a deep technical expert who thrives on hands-on problem solving and mentoring across disciplines.</p> <p> </p> <p><strong><span data-contrast="auto">Key Responsibilities</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><strong><span data-contrast="auto">Design, develop, and execute bring-up plans.</span></strong><span data-contrast="auto"> Own end</span>‑<span data-contrast="auto">to</span>‑<span data-contrast="auto">end post</span>‑<span data-contrast="auto">silicon bring up and characterization strategies, translating design/product requirements into measurable test objectives, pass/fail criteria, and schedules.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><strong><span data-contrast="auto">Drive design reviews and specification alignment.</span></strong><span data-contrast="auto"> Participate in architecture and design</span>‑<span data-contrast="auto">spec reviews to ensure testability, trace requirements to verification plans, and influence design tradeoffs to meet performance and reliability targets.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><strong><span data-contrast="auto">Lead hands</span></strong>‑<strong><span data-contrast="auto">on test execution and bring</span></strong>‑<strong><span data-contrast="auto">up.</span></strong><span data-contrast="auto"> Perform silicon block level bring</span>‑<span data-contrast="auto">up, functional and parametric testing, interop checks, and performance benchmarking; rapidly iterate on test flows to accelerate time</span>‑<span data-contrast="auto">to</span>‑<span data-contrast="auto">data.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><strong><span data-contrast="auto">Build and maintain automation frameworks.</span></strong><span data-contrast="auto"> Develop scalable test automation, data capture, and analysis pipelines to increase thr