<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><span data-contrast="auto">Job Description – </span></strong><strong><span data-contrast="auto">IP </span></strong><strong><span data-contrast="auto">Digital</span></strong><strong> </strong><strong><span data-contrast="auto">Design Manager</span></strong><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Position Overview</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">We are seeking an experienced and highly motivated Digital Design Manager to lead the </span><span data-contrast="auto">micro-</span><span data-contrast="auto">architecture, design, development, and delivery of IPs and Subsystems from for next-generation switch products. This role combines deep technical expertise with strong people leadership and program management skills.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">The successful candidate will be responsible for managing a team of </span><span data-contrast="auto">IP </span><span data-contrast="auto">digital</span> <span data-contrast="auto">design engineers while driving the successful execution of complex </span><span data-contrast="auto">IP </span><span data-contrast="auto">development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">This position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions.</span><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Key Roles & Responsibilities</span></strong><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Technology Background</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Deep understanding of complex networking protocols such as PCIE, UALink, Ethernet is a must</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Experience of working on latest generations of these protocols is highly desirable. </span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Expertise of standard front-end design flows / tools / HDLs for digital design</span><span data-ccp-props="{}"> </span></li> </ul> <p><strong><span data-contrast="auto">Technical Leadership</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Lead the end-to-end development of digital Ips / Subsystems from architecture through silicon validation.</span><span data-ccp-