<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u" data-pm-slice="1 1 []">About Astera Labs</h2> <p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor-based platforms help solve signal, data, and memory connectivity bottlenecks in the world’s most demanding computing systems.</p> <h2 class="wnfdnti _1ibi0s33y _1ibi0s34u"></h2> <p><strong>Overview</strong></p> <p>As an Astera Labs <strong>Synthesis & STA Engineer – High-Speed SerDes</strong> you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of high-speed analog/mixed-signal SerDes and connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. This role requires end-to-end ownership of logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs, deep technical expertise in mixed-signal integration, and close collaboration with analog, RTL, physical design, and verification teams to ensure robust timing closure at advanced nodes. </p> <hr> <p><strong>Key Responsibilities</strong></p> <ul> <li>Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs.</li> <li>Author, develop, and validate <strong>SDC constraints</strong> from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures.</li> <li>Set up and manage <strong>MMMC (Multi-Mode Multi-Corner)</strong> environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners.</li> <li>Drive <strong>timing closure from synthesis through sign-off</strong>, ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration.</li> <li>Define and manage I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs.</li> <li>Apply advanced sign-off methodologies at <strong>TSMC 5nm/3nm and below</strong>, including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance.</li> <li>Leverage <strong>ETM/ILM</strong> libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.</li> <li>Provide actionable timing feedback at both <strong>block and full-chip levels</strong>, including root cause analysis, timing debug, and ECO guidance for SerDes digital logic.</li> <li>Manage large-scale multi-corner/multi-mode STA runs with <strong>automation, partitioning, and efficient resource usage</strong>, developing scripts and flows to improve turnaround time.</li> <li>Generate and validate <strong>timing ECOs</strong>, partnering with physical design, analog, and RTL teams for quick closure on high-speed data-path and clock-path issues.</li> <li>Partner closely with <strong>analog/mixed-signal designers, SerDes architecture, implementation, and verification teams</strong> to drive timing convergence and provide sign-off level expertise for PHY-level and chip-level integration.</li> <li>Collaborate on <strong>clock tree</strong> and <strong>power domain</strong> strategies for SerDes digital blocks, ensuring compatibility with PLL/CDR-generated clocks and multi-supply domains.</li> </ul> <hr> <p><strong>Basic Qualifications</strong></p> <ul> <li>Bachelor's in Electrical Engineering or Computer Science required; <strong>Master's preferred</strong>.</li> <li><strong>≥8 years of experience</strong> in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.</li> <li><strong>Strong proficiency in writing and debugging SDC constraints</strong>, with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling.</li> <li>Expertise in <strong>STA methodology and timing closure</strong