<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p><strong><span data-contrast="auto">Job Title: SoC Design Manager</span></strong><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">About the Role</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">We are seeking an experienced and highly motivated SoC Design Manager to lead a team of engineers responsible for the design and development of next-generation System-on-Chip (SoC) solutions. The ideal candidate will possess strong technical expertise in digital design, excellent leadership skills, and a proven track record of delivering complex SoC projects from architecture through silicon.</span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Roles & Responsibilities</span></strong><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Technology Background</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Experience of working on complex, large SoCs on latest technology nodes under tight schedules. Exposure to chiplets is desirable.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Expertise around handling chip level design challenges around clocking, resets, power domains/distribution is a must </span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Experience of working with DFT, PD, DV teams to solve critical technical challenges of cross-domain nature</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Experience of working on PCIE, UCIE, UALink, Ethernet products is highly desirable.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="9" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Must have working knowledge of embedded processors and firmware execution to enable key SoC level features </span><span data-ccp-props="{}"> </span></li> </ul> <p><strong><span data-contrast="auto">SoC Design & Development</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Own the design and development of SoC subsystems from specification through RTL implementation.</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-ar