๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐ ๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฑ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฒ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฑ๐ฌ-๐ฒ๐ฌ ๐๐ฃ๐) Experience: 10+ yrs Location: Bengaluru We are seeking an experienced SoC Verification Technical Lead to lead full-chip System-on-Chip (SoC) verification and drive technical delivery across multiple verification projects or customer engagements. The ideal candidate will have strong expertise in pre-silicon verification, a proven track record of successful SoC tapeouts, and the ability to guide engineering teams toward high-quality verification sign-off. This role requires a combination of deep technical knowledge, verification methodology development, customer engagement, and engineering leadership to ensure functional correctness, coverage completeness, and predictable project delivery. Requirements Key Responsibilities โข Own full-chip SoC verification from test-plan development and execution to coverage closure and final sign-off. โข Verify critical SoC functionality, including boot flows, interconnects, memory subsystems, coherency, interrupts, and clock and reset sequencing. โข Lead multiple verification projects or a major customer account, ensuring technical quality, schedule adherence, and delivery commitments. โข Provide technical leadership to 6โ10 engineers through sub-leads, ensuring effective task allocation, technical guidance, and issue resolution. โข Define and standardise reusable verification methodologies, including testbench templates, Verification IP (VIP) strategies, regression infrastructure, and coverage workflows. โข Determine the appropriate distribution of verification activities across simulation, formal verification, emulation, and FPGA prototyping, coordinating with specialist teams. โข Establish and enforce sign-off criteria for functional coverage, code coverage, toggle coverage, assertions, and Gate-Level Simulation (GLS). โข Lead technical reviews, customer discussions, and escalations, communicating verification status, risks, and mitigation plans. โข Support post-silicon debugging by reproducing silicon issues in pre-silicon verification environments and identifying root causes. โข Contribute to effort estimation, project scoping, technical proposals, and Statements of Work (SOW). โข Mentor engineers and sub-leads, develop technical training materials, and participate in technical interviews. โข Improve verification productivity through automation, regression optimisation, reusable components, and AI-assisted verification flows. What Makes You a Great Fit โข 10โ11 years of experience in semiconductor design verification, with strong expertise in full-chip SoC verification. โข At least three successful tapeouts, including a minimum of one full-chip SoC tapeout. โข Proven technical leadership experience managing or guiding teams of six or more engineers. โข Strong understanding of SoC architecture, verification planning, testbench development, coverage closure, and sign-off processes. โข Experience verifying boot flows, interconnects, memory subsystems, coherency, interrupts, and clock/reset sequencing. โข Expertise in reusable verification methodologies, VIP integration, regression management, and coverage analysis. โข Understanding of simulation, formal verification, emulation, FPGA prototyping, and GLS workflows. โข Ability to define verification quality gates, assess technical risks, and drive closure of complex verification issues. โข Strong customer-facing communication, technical presentation, and stakeholder management skills. โข Experience with project estimation, scope definition, technical mentoring, and cross-functional collaboration. โข A continuous-improvement mindset, with interest in automation and AI-assisted verification to improve efficiency and quality.