Senior ASIC Physical Design Engineer

k2spacecorporation · Seattle, WA · Seattle, Washington, United States

<div class="content-intro">K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.</div>The Role  We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.   Responsibilities  <ul> <li>Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. </li> <li>Perform timing closure and optimization across multiple corners and modes using industry-standard tools. </li> <li>Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. </li> <li>Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. </li> <li>Develop and maintain scripts and automation to improve flow efficiency and consistency. </li> <li>Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. </li> <li>Assist in chip-level integration, ECOs, and tapeout preparation. </li> <li>Contribute to methodology development, tool evaluation, and flow documentation. </li> <li>Support your product through production and spaceflight.  </li> </ul> Required Qualifications   <ul> <li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. </li> <li>5–10 years of experience in ASIC physical design for complex SoCs. </li> <li>Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). </li> <li>Strong understanding of timing analysis, power optimization, and physical verifi

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